Institute of Integrated Science and Technology (IIST), a graduate program for studying integrated science and technology in English, which supports a sustainable global society, will be established at the Graduate School of Science and Engineering and the Graduate School of Computer and Information Sciences, Hosei University.


IIST Daddy Longlegs Scholarship
The 18th Hosei University IIST International Colloqium「Public Hearing of IIST Master Thesis 2020」
The 17th Hosei University IIST International Colloqium「IIST Students’ Progress Report」
The 16th Hosei University IIST International Colloqium 「Development of a Guiding Device for the Blind People」and「From Finger Tracking and Gesture Interpretation to Motion Understanding」
IIST Daddy Longlegs Scholarship
Fall Commencement 2018
IIST Daddy Longlegs Scholarship
The 11th Hosei University IIST International Colloquium「Master Thesis Report Session」
The 10th Hosei University IIST International Colloquium「State-of-the-art advancements in the field of Integrated mechano-electrical Technology」
The 8th Hosei University IIST International Colloquium「Trends in Advanced Integrated Science and Technology」

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Promotion Video

Sample Lectures

1. Prof. Genci Capi
「Intelligent Assistive Robots Operating in Real Environments」

Soon robots are expected to operate in our homes, hospitals and offices. Therefore, they have to process multiple sensors data and adapt the policy as the environment changes. In this talk, I will overview the existing efforts including our attempts at creating intelligent robots operating in everyday life environments. In particular, I will focus on remotely operating surveillance robot, robot navigation in urban environments, and assistive humanoid robot. I will show experimental results that demonstrate the effectiveness of proposed algorithms.

2. Assoc. Prof. Jinjia Zhou
「A 4Gpixel/s 8/10b H.265/HEVC Video Decoder Chip for 8K Ultra HD Applications」

8K Ultra HD is being promoted as the next-generation digital video format. From a communication channel perspective, the latest high-efficiency video coding standard (H.265/HEVC) greatly enhances the feasibility of 8K by doubling the compression ratio. Implementation of such codecs is a challenge, owing to ultrahigh throughput requirements and increased complexity per pixel. The former corresponds to up to 10b/pixel, 7680×4320pixels/frame and 120fps-80× larger than 1080p HD. The latter comes from the new features of HEVC relative to its predecessor H.264/AVC. The most challenging of them is the enlarged and highly variable-size coding/prediction/transform units (CU/PU/TU), which significantly increase: 1) the requirement for on-chip memory as pipeline buffers, 2) the difficulty in maintaining pipeline utilization, and 3) the complexity of inverse transforms (IT). This talk presents an HEVC decoder chip supporting 8K Ultra HD, featuring a 16pixel/cycle true-variable-block-size system pipeline. The pipeline: 1) saves on-chip memory with a novel block-in-block-out (BIBO) queue system and a parameter delivery network, and 2) allows high design efficiency and utilization of processing components through local synchronization. Key optimizations at the component level are also presented.